Want our tips on how to avoid unnecessary EQs, delays and poor PCB design?
Remember to ask about reliability and not only capability!
Working with customers and Design For Manufacturing the usual questions is what’s the limit?
How thin can you make 10 layers, or what is the smallest hole for this 4 mm PCB?
Very few people ask for reliability if we push hole to thickness aspect ratio to the limit, or reduce the hole wall of copper to the minimum.
The question is always: what is your capability?
In most cases it is the component footprint that brings the designer into a situation where he needs to push limits.
- Need one or more traces between the pads in a BGA area.
- Need connection from top to bottom but have very limited space through the stackup.
- Sometimes there might be a need for impedance controlled traces with a return path in the next layer, that restricts sufficient hole to copper clearance in the ground plane layer.
- Need via in pad and capped vias in a plated layer where design required too thin track and gap, leaving the PCB factory in a situation where nothing works optimal and in reality the finished PCB may have reliability issues, specially if the product needs multiple soldering operations and an application environment with elevated temperatures.
The parameters that affect reliability are not only related to design for PCB fabrication, but very much related to thermal processes and application environment.
With that background I would like to give a few examples of do’s and don’ts that brings the end product reliability in jeopardy.
Hole to PCB thickness aspect ratio
The question about aspect ratio comes up almost every week. Someone wants to know which factory has the best aspect ratio. This question brings up several questions back:
- What is the technology needed?
- How thick is the PCB?
- Which hole size is needed to design this PCB?
- How big pads can we have?
The ping pong or “chicken or egg situation”
Of course, the designer needs this to start his job, however you might find yourself in a “chicken or the egg situation”, where my questions back, lead to another question to me.
Some physics leads us to thumb of rule:
Let the factory choose the hole size based on your available pad size and the required rest annular ring according to IPC class 2 or 3.
Copper pattern to hole registration can today be easier to achieve than pushing aspect ratio. Both drilling and image accuracy have been improved greatly, while copper plating of small holes still can be a problem.
Key Learning: Insufficient copper plating in via holes is a much higher reliability risk than rest ring violations.
The effect of filled and capped vias
A change from etched layers to plated layers and in the worst case adding capped vias can bring a design from a reliable solution to a show stopper.
I had one example of a HDI 32 layer that we have tuned in by stackup to meet impedance however, the design is quite tough.
Then the designer finally says: “I need those through hole vias capped. I need “via in pad” – it is the only way to route myself out of this fine pitch BGA!” .
Wow… that ruined the whole thing. Suddenly we need another copper plating process.
Thicker copper means etching of those 75 micron traces and with 75 micron, gaps becomes impossible. Because we push boundaries we also challenge reliability.
The more processes we add to an existing tight design, the more we increase the risk for defect, either in assembly or worst case, in the final application.
In this example, it would be much better to replace the through vias with a combination of blind and buried vias.
Key Learning: Copper filled microvia is a much better solution for the fine line pattern than filled and capped through holes.
Inner layer hole to copper
In some tight high layer count designs we see that the designer removes non functional pads to give place for inner layer tracking, close to the via holes. Often this is a good solution, but be aware!
Drilling of holes in a PCB is a mechanical process that stresses the base material. As the drill bit is being used to drill many holes, the tool becomes less sharp each drilled hole until we reach the limit of acceptable roughness.
Then comes the question, of what is acceptable, and what is preferred?
We need some roughness to get a good adhesion between the copper barrel and the hole wall. But this slight roughness shall not open pores into the material that enable chemistry to enter and create what we call wicking, a conductive spike from the copper barrel and into the material.
Always remember to bring the risk factor into discussion
In the standard, IPC-6012 the size of such spikes can be up to 80 micron for class 3 and 100 micron for class 2 products. So, if we remove the pad on the inner layer to leave room for a track as close as 150 micron we are in danger. If the factory can allow 80 micron wicking and we know that hole to copper tolerance is around 50 micron (in fact often 100 micron) we suddenly are in danger of a direct contact. And, remember wicking is often a start point for Conductive Anodic Filament (CAF), and CAF comes with time.
So what can we learn from this: Use the PCB factory capability with care. Some PCB factories will warn you, but in many cases the customer is in such need of more room that the focus of discussion is on capability and not risk of failure in the application.
Key Learning: Make sure to bring the risk factor into discussion and open up for better solutions that could be replacing the through hole via with a smaller blind and buried in combination, and by that give more room for inner layer traces.
From these examples we understand that a factory capability does not necessarily mean you can go to the limit, and in the worst case combine capability limits that in reality are impossible combinations. On the other side, if you really need to push limits, make sure to ask the right questions.
Don’t just ask for technical capabilities, but make sure to discuss combinations and how your solution affects risk of failure with multiple heat cycles required to assemble the product, and the risk of failure in the final application.
Jan Pedersen, Senior Technical Advisor at Elmatica