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Do you have control of your stack up and all types of via holes?
As most people know, component holes are still highly necessary for components that require them, and clean lead-through-holes (vias) have increased in necessity over the last 30 years. They have dominated the types of holes used in a PCB. The diameter of vias has gone one way, and the complexity around via holes has generally increased.
With a continuous component hole, copper plating is not a problem; however, it requires good process control. The challenges with smaller diameter vias, perhaps depth-controlled, have increased and are, in some cases, challenging for those who produce PCBs and have to assemble and handle solder components.
Via holes in the PCB are highly necessary to be able to carry out the number of connections required. In general, the via holes of today can be briefly summarized as follows:
- Through: Mechanically drilled holes
- Blind: Mechanical depth-controlled drilled holes
- Blind: Laser vias
- Buried: Mechanically drilled vias
- Buried: Laser vias
- Back-drilled via holes
- Half/castellated holes
In addition, laser vias may be stacked or staggered relative to each other, and they may also be stacked or staggered relative to a buried mechanical hole.
Furthermore, laser vias, blind, and mechanically drilled through-holes can be placed in component pads (SMD pads), which requires special treatment.
Laser vias can be copper-filled or filled with resin. If they just act as fan-out vias, they are simply covered with the solder mask used. When filled with resin, they can also be capped with copper, and then components can be mounted and soldered directly on them. Copper-filled laser vias is the latest method used, but both methods are still very relevant.
PCB manufacturers operate with their own capability in terms of diameter, aspect ratio (AR), and pad diameter requirements on the various hole variants. The problems related to production are mostly the same with all manufacturers, but processes, equipment, technologies, etc., are the reason for PCB manufacturers to have a difference in capacity and capability. This is also reflected in the fact that some PCB manufacturers have specialized in prototypes and small, fast deliveries, while others are specialists in high volumes.
Considerations for Designers
It is essential that designers become familiar with the production processes so they can understand what is possible and not possible to produce. Some who were not aware previously operated with a through-hole diameter of 0.1 mm on 2-mm thick PCB. Fortunately, there are not many left, but some are still out there.
For a PCB to be produced with a good result, it is important to provide the designer with this information on capability and design rules. However, the designer must also be obliged to obtain the necessary information before starting a layout. This is absolutely essential for a good result.
As a designer, you must have access to the current IPC standards that the world’s manufacturers adhere to—typically, IPC-6012, IPC-6013, and IPC-A600. However, the designer must also clarify what is available in relation to the type of PCB that is to be realized. I have mentioned in previous columns how important this is, as the cost of redesign due to lack of knowledge about the rules that apply is not something you want to cover.
Laser Vias Used in HDI PCBs
HDI PCBs are an increasingly integral part of the PCB and electronics industry in general. Electronic components are getting smaller and lighter but still require high performance. To meet this, you also need to pack more functionality in a smaller area with HDI PCBs.
HDI PCBs have a higher circuit density per unit than conventional PCBs. They use a combination of buried and blind vias, as well as laser vias. Those that are ≤0.15 mm in diameter are also called microvias (mVias).
Any Layer HDI, ELIC, and ALIVH
High-density PCBs have a combination of different vias, as compared to others that only have laser vias and tend to be called any layer HDI. Other names are every layer interconnect (ELIC) HDI and any layer interstitial via hole (ALIVH).
The maximum number of layers with this technology I have seen is 14 layers. Then, you have a finished PCB with stacked laser vias and a maximum thickness of around 1 mm. This anonymous stackup is one I have worked on, but I do not have permission to show this stackup, so Figure 1 and Table 1 show an equivalent of eight layers and is about 0.6-mm thick.
Figure 1: Eight any layer stackup.
Table 1: Eight any layer impedances.
The most common combination of vias in an HDI PCB is 1–3 sets of laser vias per side, in combination with mechanically drilled buried vias. Through-holes are for components that require this, as well as unplated holes.
Via holes that go from top to bottom have been replaced with the combination of laser and buried holes already defined. This avoids a potential overplating of the outer layers as a result of a longer plating time in order to obtain a solid copper plating in small via holes with a high AR.
Three Variations of Laser Vias With Different Combinations
Figures 2 a, b, and c show some combinations. For all three combinations, laser vias on the top (layers 1–2) and bottom (layers 14–13) are copper filled as they are placed in the SMD component pad; thus, they are soldered. Figure 2a is the least challenging in terms of copper plating and also the most reliable and lowest cost to produce.
Laser vias on layers 2, 3, 12, and 13 are staggered and filled with resin after electroless copper, electrolytic copper plating, and etching. The same goes for the buried hole layers 3–12, often filled with epoxy.
In Figure 2b, all laser vias are filled with copper and stacked on top of each other. There is a cost for copper filling of the inner laser vias, and the reliability of stacked vias is lower than in Figure 2a where they are staggered. The big change in Figure 2c, compared to 2b, is that laser vias are stacked on the buried hole (layers 4–11). The buried hole is now also clad with copper to secure the connection to the laser via, which is placed directly on top.
Of the three examples, Figure 2c has the highest cost and is also less reliable than Figures 2a and 2b. The lower reliability in Figures 2b and 2c is based on a potential expansion of the material in stackup that may affect the connection between the vias that are directly connected to each other. In certain cases, electrical properties must be prioritized, and lack of space can also be the reason why an extended stacked vias solution is chosen.
Figure 2a: 14-layer stackup, example 1.
Figure 2b: 14-layer stackup, example 2.
Figure 2c: 14-layer stackup, example 3.
In certain situations, there may be up to three copper platings on some layers. This is related to conditions such as copper filling of laser vias, overplating of mechanically drilled vias, and the plating of through-holes. This can create challenges for the subsequent etching of narrow conductors, which is a concern with HDI PCBs today.
The amount of copper plated in the various holes is, in most cases, specified in IPC standards that PCB manufacturers and end customers adhere to. You get a full overview—including the complete standards, tables, and illustrations—on IPC’s website, but here are some values from IPC-6012E.
|Class 1||Class 2||Class 3|
|Copper—Average||20 µm||20 µm||25 µm|
|Thin Areas||18 µm||18 µm||20 µm|
Table 2: IPC-6012E Table 3-4 Surface and Hole Copper Plating Minimum Requirements for Buried Vias >2 Layers, Through-Holes, and Blind Vias.
|Class 1||Class 2||Class 3|
|Copper—Average||12 µm||12 µm||12 µm|
|Thin Areas||10 µm||10 µm||10 µm|
Table 3: IPC-6012E, Table 3-5 Surface and Hole Copper Plating Minimum Requirements for Laser Vias (Blind and Buried).
|Class 1||Class 2||Class 3|
|Copper—Average||13 µm||15 µm||15 µm|
|Thin Areas||11 µm||13 µm||13 µm|
Table 4: IPC-6012E, Table 3-6 Surface and Hole Copper Plating Minimum Requirements for Buried Cores (2 Layers).
|Class 1||Class 2||Class 3|
|Copper Cap—Minimum Thickness||AABUS||5 µm||12 µm|
|Filled Via Depression (Dimple)—Maximum||AABUS||127 µm||76 µm|
|Filled Via Protrusion (Bump) —Maximum||AABUS||50 µm||50 µm|
Table 5: IPC-6012E, Table 3-11 Cap Plating Requirements for Filled Holes.
How to Avoid Layout Rejections
Every week, we receive many layouts that are rejected long before they end up in PCB production. The main reason is that they contain design issues that have not been clarified with the PCB manufacturer before the design begins, or the design is not in accordance with IPC requirements.
Typical conditions are:
- There is too great a distance between the layers where laser vias are used.
- The copper is too thick in relation to the conductor widths to be etched and the distance between them.
- The designer has not calculated that inner layers can also be plated when laser vias and buried holes are used.
- The AR is incorrect, which especially applies to smaller drilled holes. The recommended
maximum AR is 8:1 on buried and through-drilled holes. Laser vias have a recommended maximum AR of 0.8:1.
- There is a misunderstanding of the use of laser vias, often defined as through-holes with a 0.1-mm diameter.
Resolving the Layout and Making It Producible
In these cases, we open a dialogue with the designer and give them an introduction and recommendation on how their design can be made producible. Vias plays an important role in a PCB as signal speeds increase. A PCB designer must be able to handle this. In general, we can say that vias constitute a discontinuity in the transition from a conductor and will affect the signal in designs with high-signal speeds.
Capacitance can increase rise time, which reduces speed. Therefore, designers must ensure a good impedance transition. The larger the pad diameter, the lower the impedance due to the increased capacitance. By removing non-functional via pads on the inner layer, the capacitance can be reduced.
A dangling via stub acts as an open resonator. When using laser vias, we have no stub. On traditional drilled vias, a stub can be removed with back-drilling.
Drilled Via Hole Reliability
The reliability of drilled via holes is affected by several parameters:
- A reduction in the length of the hole will make the hole more reliable, which can be done by reducing the total PCB thickness or reducing the length of a buried hole.
- An increase in the diameter of the hole can also provide increased reliability, but this is typically a non-option due to lack of space. For example, 0.2–0.25 mm can provide increased reliability.
- The choice of material—especially the coefficient of thermal expansion (CTEz) and
and elastic modulus or stiffness (Ez)—also contributes to increased reliability, but Ez is not mentioned on all datasheets.
In materials, there is a different mix of glass and resin. Previously, it has been the practice that the properties for laminate and prepreg stated in the datasheet are for the type with the thickest glass, type 7628, but this is now beginning to be nuanced a little more. This is good because, typically, the most advanced PCBs use prepreg with the lowest glass content—glass styles 106 and 1080.
The CTEz expressed in ppm is approximately 25% higher for a 106 (thinnest) prepreg than
for a 7628 (thickest). For Ez, which is measured in megapascal (MPa), then the typical value for 106 prepreg is around 4300; for 7628 prepreg, it is approximately 5,800. Resin content in a 106 prepreg can be well over 70%, while in 7628, it is down in the range of 42%.
For an EMS or others who will assemble components and solder them, it is important that they also understand a stackup and know what challenges they may have to solve. I am thinking in particular that a number of copper-filled buried vias directly into the BGA footprint is something that they should know about, and it will help them determine a good soldering profile.
Early Involvement, Lower Cost
I have been in the industry of printed circuits for ages and deal with layouts and PCB design every day. Vias play an important part of the PCB, so it’s important to know what they are, how they work, and how to solve any challenges involving them. My job is to advise on design, solve EQs, and ensure all parameters are covered early in the design process. The earlier we talk and discuss, the fewer the mistakes and the lower the cost for avoiding expensive redesign.
Here are the top five things to remember about vias:
- Be sure to stay updated with the latest IPC standards relevant for your design and need.
- Make sure you have the AR in place.
- Make sure the pad diameter is sufficient. Remember that the unprocessed hole is drilled around 0.1 mm larger than the nominal diameter. For laser vias, the unprocessed hole is <0.1 mm.
- Use stacked laser vias only if needed. Otherwise, they should be staggered.
- Only use stacked laser vias on top of buried holes when needed.
The last advice from me might sound simple but is crucial: It is important that you discuss design requirements with your PCB supplier and make sure that you understand each other and agree on the way forward.
John Steinar Johnsen is senior technical advisor at Elmatica and one of the PCB Norsemen.
This article was first published in I-Connect 007 PCB Magazine. To read past columns or contact The PCB Norsemen, click here.