John Steinar Johnsen at Elmatica

Josses Corner: What to think about when planning a PCB – signal integrity/controlled impedance

Josses Corner: What to think about when planning a PCB – signal integrity/controlled impedance

Knowledge and experience – two key elements when planning a PCB.  Todays PCB designers must, in my opinion, have more knowledge on the PCB production than before. Especially when they plan, and how they plan stack up, via span, routing and power distribution.

I will in this article focus on multilayer boards since this is the type of PCBs where we truly see the importance of planning, in the day to day PCB life. On a double sided board you can, of course, use one layer as a ground plane, but critical traces are not easy to handle.

As a designer, you know your needs when it comes to signal integrity, EMI (electromagnetic interference) design and impedance requirements.  The factors involved are of course:
– number of layers
– the number of power and ground planes that you will use
– the sequence of layers
– the space between the layers.

To continue this we can say that
– signal layers carrying critical signals should always be adjacent to a plane
– power and ground planes should be as close as possible for best capacitance
– power and ground planes can use other material with a higher Dk, for best possible capacitance
– High-speed signals should be routed on inner layers located between planes for best possible
 shielding
– multiple groundings will lower the reference planes impedance, and reduce the common
 mode radiation from the high-speed signals.  

The lowest layer count you need to achieve all of this is probably an 8 layer board. See Figure 1.

 

Figure 1. Sample on an 8 layer stack up.

However, above-mentioned points can be very challenging. There might be a maximum thickness of the PCB that cannot be ignored, many plane layers will limit the number of signal layers. It can be difficult to get the wanted signal impedances, ref to distance between layers, track widths and gaps between tracks.

Signal integrity addresses the degradation of signal quality to the point where an error occurs.  EMI focuses on the corresponding specifications, test requirements and interference between nearby equipment.

Ground impedance is the root of virtually all signal integrity and EMI problems. To keep a low ground impedance is mandatory for both EMI and signal integrity.
This is achieved with a solid ground plane.

Copper thickness is not an important factor.  At high bitrates, the skin effect dominates so the signal is pushed to the copper surface, which means that additional copper thickness is irrelevant.

For signal integrity, the key factor is to keep noise levels significantly below signal levels. Our noise margins are typical in the millivolt range for digital circuits, but for EMI, emission levels must be kept in the microvolt and microamp range.

In fact, the main problem with ground impedance is the discontinuities that occur in the signal path, and it has a major impact on characteristic impedance control.

These days with more and more HDI designs operating well up in the GHz frequencies, characteristic impedance control becomes more important, but also more challenging to maintain, since distances between layers are chinked.  HDI and use of microvias require less distance between layers and the fact that more layers will be squeezed within a given PCB thickness.

The biggest problem with maintaining impedance control is the signal path discontinuities, including the return path on the ground plane. Ideally, there should be a copper plane immediately underneath critical signals and the signal should refer to this ground plane without interruptions.  Worst scenario (Figure 2) can be if the signal is leaving the ground plane and continues e.g. along a voltage plane.

 

Figure 2: Return path shown in yellow. Discontinued if switching planes.

It is less problematic if the signal goes through the GND plane and continues on the other side of the plane (Figure 3). There is no issue with the reference GND since it is the same, just make sure that vias are kept as small and short as possible. The keep out diameter around the vias shall also be kept at a minimum.

 

Figure 3: Return path shown in yellow. Reduced Discontinued if kept to the same plane.

There can also be cuts in the plane such as too large anti pads (Figure 4). In the shown sample the half of a differential pair is exposed over a missing plane. The result is unbalanced current flow, delays in signal propagation delays, increased series inductance.

Figure 4. Unbalanced differential pairs due to too wide openings in GND plane and or signals routed too close to the pad.

Cuts in the plane, as shown in Figure 5, shows a discontinuity in the signal return current path. The return path has to go all around the gap in the plane. This will raise the characteristic impedance at the gap, and the opening can end up as an antenna. The sample shows a split plane where other signals are routed in the plane opening.

 

Figure 5. Disrupted return path due to the cutout in the GND plane. Return path will go around the cutout.

Let’s talk about Crosstalk
Another issue for both EMI and signal integrity is Crosstalk. Crosstalk is a coupling to adjacent signals, GND or PWR connection that is unintended. Crosstalk is normally seen as a major problem with cables, but it can also occur at the PCB level. Increased space between critical lines is normally the solution. And in some cases space can be used for less critical lines. Increased spacing is in general very beneficial when coupling falls off with the square of the insulation distance. Increasing distance due to crosstalk can also be an issue in Z-axis of the PCB.

When a new PCB design is to begin, designers should start communication with manufacturers at a very early stage. Start with the name /number of the PCB, then the following communication can be linked where it belongs. Do not communicate other PCBs in the same email/ticket. Unfortunately, this happens often and causes unnecessary misunderstandings and extra work.

When you as a designer need a stack up to start routing, there is some information that you need to pass on to the engineers at the PCB manufacturer, so they have a base to start on.
What you will get back is a stack up with values on your impedance traces, that you can use in your CAD software.

The strengths of PCB manufacturers have traditionally been:
– PCB material knowledge
– lamination
– drilling
– plating
– etching
– surface treatment
– mechanical finishing

Time has changed and electrical engineering is now part of what you get from the manufacturer. Electrical requirements as Impedance, plane capacitance, crosstalk and electrical testing is the knowledge that you find in the Engineering departments of the PCB manufacturers who can handle advanced PCBs.
This, in combination with your own knowledge and skills, is the best combination for a successful stack up and well working PCB.  
The knowledge on how e.g. different laminates, types of glass styles and resin content percentage works in the production process, are examples of knowledge PCB manufacturers know the best.

What to do when you need a stack up with impedance requirements:

Figure 6. Example customer stack up

 

Above you see a sample stack up. Figure 6,  reflects the drill and via span in a stack up, information a manufacturer must get before setting up a final stack up for you. This information tells the manufacturer that the following layers will be copper plated in addition to the etching. And that some layers also may need to be plated 2-3 times, if there is a combination of mechanical and laser holes. It also informs that eventual holes shall be copper capped as well.
The above illustration also tells the total numbers of layers and where signal and plane layers are located.

In addition, the following information is needed:
– Final thickness of the PCB
– What impedances that are present on the various signal layers (Single End and Differential
 pairs) and their reference layers.
– Preferred minimum track width. This is valid information for manufacturers, to give the right
 values back for track widths, due to HDI and or fine pitch components used
in your PCB.
– If there are minimum distances between layers, due to crosstalk or other electrical reasons
– If you have preferred materials, it can be dedicated materials or materials locked to a
 IPC 4101/(under group), you should mention it.
– Total Size of the PCB.

What you can expect back from the manufacturer is a:
– Complete stack up, with copper and dielectric thicknesses, BOM (Bill of materials)
– Track widths that you shall use on your impedance traces
– Space to use between the impedance traces (differential pairs)
– Calculation of the results above.
You can now start your layout.

Just a little tip
A tip: Make your impedance traces visible for the manufacturer.

You can have most connections routed with e.g. 100µm, and if there are some single end traces using the same width, the manufacturer can not separate these from the others.  What you can do, is to set the width of the critical single end traces to a slightly higher or lower value. E.g. 99µm or 101µm.
This change is so small that it has no influence on the production, but it will now be possible for the manufacturer to separate these traces from the others.

As a designer, you shall know that the stack up you have received from your manufacturer, with values used for your routing, is NOT final.
At the stage where your layout is ready and you want your PCB produced, there will in most cases be some technical issues on impedance values, asked from the PCB manufacturer.
These are caused, for obvious reasons, by the fact that manufacturers do not have access to your production data (Gerber, ODB++, IPC 2581….) at the stage when the stack up is done.


Copper percentage – influence the prepreg
When manufacturers have received your production data, they will also e.g. calculate the percentage of copper you have used on your signal and plane layers. This will influence the types and prepregs to be used and will affect impedances.

The manufacturer will inform you via Technical Queries that some changes will be done for you to get your requested impedances.  These changes will normally be very marginal changes on track widths, gaps or layer distances, and will in most cases be accepted without too much arguing.
If there should be a change in the prepregs that will lead to a change in the resin content, this will also change the Dk value and will be taken into consideration when impedances are re-calculated.  

For the designer, it is most important to get requested impedances, and when it comes to these minor adjustments, I consider manufacturer to know best what to do.

I often compose start stack-ups for designers, and the tool I often use is ICD Stackup planner from ICD.com.au. What we experience used by most PCB manufacturers, is the software from Polarinstruments.com

My tip to you is: Get started, communicate with your PCB manufacturer and do not forget to include a netlist with your PCB production data. Enjoy the wonderful world of printed Circuits!

This article was published first time on our company column – The Norsemen in the PCB Magazine

Thanks to iCD for allowing us to use their illustrations.

 

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